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25 August 2006
Agile Hardware Design?

Looking back at my first semester thesis at ETH , where I designed a full-custom ASIC , I realize something odd: In VLSI design, especially when designing ASICs or ASIPs (not so much on FPGAs), people make a real fuss about testing . For a good reason, since A) the fabrication setup is expensive and... Read More...

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Filed under: ASIC, Thesis, Hardware, Agile, VHDL